Program 2025 - DAY ONE *
3 Days – 9 Thematic Focus Tracks – 100 Percent Knowhow
08:20 - 08:30 am
Welcome Session
Let's meet in the exhibition area in front of the main stage for the welcoming words to the FPGA Conference Europe 2025.
Maria Beyer-Fistrich
Editor-in-chief | ELEKTRONIPRAXIS
Stefan Krassin
CEO | PLC2
08:30 - 08:55 am
OPENING SPEECH
Powering the Future – How Low Power FPGAs are Shaping Tomorrow's Tech Landscape
Senior Vice President of Research &
Development | Lattice Semiconductor
Description
In the rapidly evolving technology landscape, low power Field-Programmable Gate Arrays (FPGAs) are emerging as essential components driving innovation across various sectors. This keynote presentation will delve into the market dynamics and trends that are positioning low power FPGAs at the forefront of technological advancements, and how Lattice Semiconductor is infusing today’s top industries with efficient, intelligent, connected, and secure solutions.
9:00 - 9:40 am
HFM – The First Open FPGA Standard is Taking Shape | Application
Standardization Group for Embedded Technologies (SGET)
Description:
The Harmonized FPGA Module (HFM) is set to become the first open standard tailored specifically for FPGA and SoC-FPGA System-on-Module (SoM) designs, offering unparalleled flexibility and adaptability. Developed by the Standardization Group for Embedded Technologies (SGET), this innovative standard introduces an open and harmonized approach, allowing for an almost seamless choice between solderable and connector-based modules. This dual-option framework addresses a wide range of design needs, from high-speed data processing to space-constrained environments, ensuring that common interfaces remain consistent across both physical formats.
The presentation will highlight the essential goals of HFM, including its modular support for low- to mid- and high-performance FPGAs, enhanced security and signal integrity, and streamlined manufacturing advantages. For the solderable modules (s.HFM), features such as direct PCB soldering increase reliability, while the compact design enables use in applications with strict space limitations. The connector-based variant (c.HFM) focuses on high-performance support, including robust thermal management and simplified prototyping.
The HFM standard stands out by fostering a collaborative ecosystem of hardware and software where FPGA designs are optimized, scalable, and more accessible. The presentation will address discussions on challenges and how the standardization team has solved them in their HFM approach to help shape this groundbreaking open standard and drive new efficiencies in FPGA applications across industries.
Level: Intermediate
FPGA Verification and Testing | Language / Debug / Verification
Arrow Central Europe GmbH
Description:
Discussing methodologies and tools for verifying and testing FPGA designs, ensuring reliability and correctness. Various verification strategies, including simulation-based verification, formal verification, and hardware emulation, highlighting their strengths and limitations. Provide insights into developing effective test benches, including the use of self-checking testbenches, stimulus generation, and testbench automation. Present FPGA prototyping as a verification methodology, allowing the design to be tested in a more realistic environment before final implementation. Address strategies for regression testing and automation, ensuring that verification tests are continuously applied as the design evolves. Present common challenges faced in FPGA verification, such as handling complex designs, managing simulation time, and ensuring comprehensive coverage.
Level: Intermediate
Firmware Architecture for FPGAs | Architecture
plc2 Design GmbH
Description:
Starting a new FPGA design from scratch is a chance to build a reliable and rock-solid foundation for many upcoming design
iterations or requirement changes. This presentation will show best practice how PLC2 sets up an FPGA design in VHDL.
Level: Beginner
Welcome to the Post-European Cyber Resilience Act (CRA) Era | Safety & Security
Avnet EMG AG
Description:
In this new landscape, your FPGA-based products must incorporate security concepts by design. Here's the reality:
- Security adds no direct benefit to your product's functionality.
- Security increases design and production complexity.
- Security negatively impacts system performance (e.g., boot time, file I/O).
- Security is a pain, really But there’s no way around it - and for good reasons.
The CRA was established to ensure robust Cybersecurity standards across the industry. Secure boot and measured boot might be essential components to help your AMD-based products comply with the CRA. Join us for this 90-minute session, divided into four key topics (with a short break):
- Overview of the CRA A brief introduction to the Cyber Resilience Act and its implications.
- Why Security Matters: A Practical Example Through a live demo, we’ll show why security is crucial: We'll copy the main flash content of an AMD Kria SoM to a PC, inject malicious code without adding files to the root file-system, and copy it back. Curious about what the injected code does and how it works? Join us to find out
- Trusted Platform Module (TPM) An in-depth look at TPM concepts with a live demonstration on the AMD Kria SoM: Root file encryption using LUKS, with the decryption key unsealed from the TPM. Implementing PCR policies to detect unauthorized software changes in early boot stages (FSBL, U-Boot, Kernel).
- Secure Boot A step-by-step guide on:- Generating RSA keys and signing the BOOT.BIN image.- Burning eFuses on an AMD Zynq UltraScale+ device for secure boot.
Level: Intermediate
Duration: 90 mins
Vitis AI for Versal AIE-ML and Versal Gen 2 | AI / ML
plc2 GmbH
Description:
The edge-acceleration of neural networks is a growing demand in industrial and commercial designs. To leverage a vertical design flow for the processing of network models the Vitis AI toolchain picks up from pre-trained models of various modeling frameworks and maps the computation out to a scalable IP, the Deep-Learning Processing Unit (DPU). With the flavors of Versal AI Engines as vector processing elements the DPU also exists in different variants. This talk describes these differences and hints on the upcoming
Versal Gen 2 version. The AIE and AI-ML type DPUs will serve as a basis to understand the benefits and the approaches to tackle mapping of CNN models with Vitis AI along the revisions.
Level: Beginner/Intermediate
Design of an UART | Tutorial
plc2 GmbH
Description:
The tutorial consists of four parts and is aimed particularly at beginners and those who would like to deepen their FPGA knowledge. The tutorial is divided into four separate parts, each covering different aspects of the entire project.
Design:
- Design of a UART
- Design of a simple command interpreter Verification (Test Bench)
- Modeling the laptop connection (UART)
Hardware testing
Level: Beginner
Duration: 90 mins
9:40 - 9:50 am
Short Break and Option to Change Rooms
9:50 - 10:30 am
Efficient FPGA Development and Beyond | Application
Emerson
Description:
The presentation highlights proven tools and methods for FPGA development, illustrated through industrial projects at Emerson. It introduces approaches for IP development, core extension, and interface design using new tools such as HxS and SimStm. Additionally, it emphasizes their application in current projects.
Level: Beginner
Live Design Investigation | Language / Debug / Verification
plc2 Design GmbH
Description:
Let's open a ≈300 MiB Vivado design checkpoint and look what is inside. This live demonstration will run Vivado reports and
investigate a real Zynq Ultrascale+ ZU19 design.
Level: Beginner
Don’t! - Frequently Encountered FPGA Design Quirks you Better Avoid | Architecture
FH Oberösterreich Studienbetriebs GmbH
Description:
With over two decades of experience in consulting companies on FPGA design and having taught VHDL-based FPGA and ASIC design to more than 1,000 students, the author continues to encounter recurring challenges in FPGA design. This talk aims to highlight some quite basic, but still common
pitfalls and misconceptions in FPGA design, including:
- "They told me to avoid latches. I only get a single warning among 179 others. Why should I bother?"
- Saving resources (and inviting trouble): Using the asynchronous reset to zero a counter when it hits its upper limit.
- The asynchronous reset: Why you shouldn't leave it as asynchronous as it is.
- Is Timing Analysis essential, optional, or automatic? Subtitle: Have you ever written an .sdc or .xdc file?
- The clock is running too fast. What to do? Strobe signals, gated clocks, or generating a slower clock from the faster one?
- Synchronizing needs a single flip-flop. Right or wrong?
- “VHDL provides the function rising_edge() to detect rising edges in the design.” Why should I spare it for clock signals only?
Join us as we delve into these topics and provide insights on how to avoid these common design issues, ensuring more robust and reliable FPGA implementations.
Level: Beginner
Welcome to the Post-European Cyber Resilience Act (CRA) Era | Safety & Security
Avnet EMG AG
Description:
In this new landscape, your FPGA-based products must incorporate security concepts by design. Here's the reality:
- Security adds no direct benefit to your product's functionality.
- Security increases design and production complexity.
- Security negatively impacts system performance (e.g., boot time, file I/O).
- Security is a pain, really But there’s no way around it - and for good reasons.
The CRA was established to ensure robust Cybersecurity standards across the industry. Secure boot and measured boot might be essential components to help your AMD-based products comply with the CRA. Join us for this 90-minute session, divided into four key topics (with a short break):
- Overview of the CRA A brief introduction to the Cyber Resilience Act and its implications.
- Why Security Matters: A Practical Example Through a live demo, we’ll show why security is crucial: We'll copy the main flash content of an AMD Kria SoM to a PC, inject malicious code without adding files to the root file-system, and copy it back. Curious about what the injected code does and how it works? Join us to find out!
- Trusted Platform Module (TPM) An in-depth look at TPM concepts with a live demonstration on the AMD Kria SoM: Root file encryption using LUKS, with the decryption key unsealed from the TPM. Implementing PCR policies to detect unauthorized software changes in early boot stages (FSBL, U-Boot, Kernel).
- Secure Boot A step-by-step guide on:- Generating RSA keys and signing the BOOT.BIN image.- Burning eFuses on an AMD Zynq UltraScale+ device for secure boot.
Level: Intermediate
Duration: 90 mins
Automating FPGA System Design Using Generative AI Agents Within Xilinx Vivado IP Integrator | AI / ML
Intelligent Edge Systems
Description:
Field-Programmable Gate Arrays (FPGAs) have revolutionized high-performance computing, embedded systems, and AI acceleration by offering reconfigurable hardware optimized for specific tasks. However, FPGA design remains a complex, time-consuming process requiring significant expertise. Traditional design workflows involve manually selecting Intellectual Property (IP) cores, configuring them, and interconnecting them using tools like Xilinx Vivado IP Integrator. These tasks demand deep domain knowledge, iterative tuning, and extensive debugging, making FPGA adoption challenging for many developers. With the rise of artificial intelligence, particularly generative AI, there is an opportunity to automate FPGA system design by leveraging intelligent agents. This talk explores a novel AI-driven approach to automating FPGA IP-based designs, streamlining development cycles, and optimizing hardware configurations within Xilinx Vivado.
Level: Expert
Design of an UART | Tutorial
plc2 GmbH
Description:
The tutorial consists of four parts and is aimed particularly at beginners and those who would like to deepen their FPGA knowledge. The tutorial is divided into four separate parts, each covering different aspects of the entire project.
Design:
- Design of a UART
- Design of a simple command interpreter Verification (Test Bench)
- Modeling the laptop connection (UART)
Hardware testing
Level: Beginner
Duration: 90 mins
10:30 - 11:15 am
Coffee Break and Visit of the Exhibition
11:15 - 11:55 am
The PoC Library - Open-Source VHDL Component Library "Pile of Cores" | Application
Patrick Lehmann & Stefan Unrein
plc2 Design GmbH
Description:
The PoC Library is a free and open-source platform-independent VHDL package and component library. While the public version of PoC did not receive much care over the years, PLC2 has added many new features and components. The PoC Library is now maintained by the Open Source VHDL Group (OSVG) and PLC2 will contribute updates
step-by-step in the next months. This first part of our presentation will introduce The PoC Library and its benefits. We will also outline the roadmap of PLC2’s upcoming contributions.
Level: Beginner
Getting Started with OSVVM | Language / Debug / Verification
SynthWorks Design Inc
Description:
The goal of Open Source VHDL Verification Methodology (OSVVM) is to simplify your testbench and increase your productivity by providing advanced verification capabilities that can be incrementally added to your current testbench. With OSVVM, any VHDL engineer can write VHDL testbenches and test cases for both simple unit/RTL level tests and complex, randomized full chip or system level tests – and have fun doing it.
This presentation is a brief overview of adding OSVVM capabilities in your current testbenches. It will provide an in-depth discussion on:
- Transactions
- OSVVM testbench structure
- Self-Checking
- Log messages
- Randomization
- Scoreboards
- Functional Coverage
OSVVM is developed by the same VHDL experts who have helped develop VHDL standards. We have used our expert VHDL skills to create advanced verification capabilities that are simple to use and work like built-in language features.
Level: Beginner
The Next Generation SoC FPGAs is Here! | Architecture
HandsOn Training
Description:
Major FPGA vendors are used to integrate ARM CPUs in their FPGAs. The Agilex 5 SoC FPGAs are based on ARMv8.2-A Architecture which is built on DynamIQ technology, and integrate the dual core Cortex-A55 & dual core Cortex-A76 CPUs. DynamIQ brings a new technology architecture that changes the landscape of heterogeneous processing. It features the latest Armv8-A architecture extensions that introduce new NEON instructions for machine learning, advanced safety features and more support for Reliability, Accessibility and Serviceability (RAS). This talk introduces the DynamIQ technology as well as the Cortex-A55 & Cortex-A76 CPUs, their new capabilities over the previous generation (Cortex-A53/A72).
Level: Beginner
FPGAs and the Cyber Resilience Act | Safety & Security
AMD
Description:
With the introduction of the European Union's Cyber Resilience Act (CRA), industry needs to comprehend the impact on their products for compliance to the new act. The CRA applies to all products with digital elements ("PDEs") that are connected either directly or indirectly to another device or to a network. Approximately 90% of PDEs are expected to fall into the Default Category, which allows for provision of a Declaration of Conformity through self-assessment. As FPGAs, Microprocessors and Microcontrollers with Security features are specifically listed in the CRA as Class I (Important Products). The CRA requires that Class I products be assessed at a minimum to forthcoming harmonized standards. However, at the time of writing, the necessary harmonized standards and delegated acts providing the details required for certification are not available.
This presentation will provide AMD AECG’s view as to the current status of the CRA, associated harmonized standards, and delegated acts as they apply to FPGAs and associated tools, providing the audience with the latest update on the work AMD is doing to ensure continued availability of FPGA products post CRA enforcement.
Level: Intermediate
Designing AI Solutions with Lattice for Real World Applications | AI / ML
Lattice Semiconductor
Description:
Designing AI solutions with Lattice FPGAs for real-world applications leverages their low power, high performance, and parallel processing capabilities. Lattice’s sensAI stack simplifies development with pre-verified IP cores, reference designs, and software tools, enabling efficient implementation and optimization of AI models.
Discover the journey of designing AI systems with Lattice devices through the learnings from various real-world customer applications. This session offers a special focus on a Sichuan pepper sorting system, which utilizes AI with Lattice devices to provide a low latency and reliable real-time application.
Level: Intermediate
Design of an SPI CONTROLLER to Control External DACs | Tutorial
plc2 GmbH
Description:
Design:
- Design of Wave Form Generator
- Design of an SPI CONTROLLER to control external DACs Verification (Test Bench)
- Modeling the external DACs
Hardware testing
Level: Beginner
Duration: 90 mins
11:55 am - 12:05 pm
Short Break and Option to Change Rooms
12:05 - 12:45 pm
The PoC Library - Open-Source Universal AXI4-Lite Register | Application
Patrick Lehmann & Stefan Unrein
plc2 Design GmbH
Description:
In the second part of our presentation about The PoC Library, we will present our universal AXI4-Lite register implementation. We will demonstrate basic features like read-only registers as well as advanced modes like sticky interrupt registers or atomic operations. As an example, we will explain our axi4lite_GitVersionRegister, which contains up-to-date Git information collected at every synthesis run.
Level: Beginner
OSVVM, the New And More Recent Updates | Language / Debug / Verification
SynthWorks Design Inc
Description:
Open Source VHDL Verification Methodology (OSVVM) has continued to grow in capability through the years. This presentation reviews the more recent updates to OSVVM such as VHDL-2019, Settings, Co-Simulation, Requirements Tracking, Data Structure Updates, Script Updates, Generic Handling, Report Updates, and additional items to small to list.
While some updates happen due to our own internal vision, others are generated by user requests. You can request updates by:
- posting an issue on GitHub - https://github.com/OSVVM/OsvvmLibraries (preferred)
- asking questions on OSVVM.org forums
- Sending email to Jim Lewis (note these occasionally get lost)
OSVVM also accepts user authored updates via pull requests on the dev branch of our GitHub repository.
Level: Intermediate
Key Criteria for Choosing an RFSoM | Architecture
Knowledge Resources GmbH
Description:
RFSoMs (Radio Frequency converter enabled Systems on Module) are convenient. They take care of all the FPGA’s complex power requirements and memory interfaces, are typically compact and save months, if not quarters in development time. But are they any good? Will you get the same RF performance as you might in a carefully designed chip-down approach. YES — if you source well designed modules. This module highlights the main points to watch out for when choosing your SoM ... or designing your own solution.
Level: Beginner
Cyber Resilience Act: Planning your Security Future | Safety & Security
Martin Kellermann & Brian Colgan
Microchip Technology
Description:
The European Cyber Resilience Act is ratified and the clock is now ticking to integrate security into connected digital systems in an auditable way. How does this apply to your system using FPGAs or SoCs? Designs must be without “known vulnerabilities,” and this might be a danger for some FPGA architectures. Security updates must be provided for several years after introduction of the product into the market, are your designs set up to handle this and allow enough updates to your encryption keys to exchange as required?
What secure and authenticated update-mechanisms are available, what tamper-detection mechanisms are available and how would you employ these? This session will talk about security-features in PolarFire® FPGAs and SoCs and how you can utilize these to keep your security-shields up over the lifetime of your product.
Level: Intermediate
Deploying Edge AI Applications with Lattice sensAI AI Solution Stack | AI / ML
Lattice Semiconductor
Description:
The Lattice sensAI AI Solution Stack is designed to simplify the deployment of AI and machine learning (ML) models on edge devices, leveraging the low power and flexibility of Lattice FPGAs. This solution stack includes a comprehensive set of tools and resources, such as modular hardware platforms, example demonstrations, reference designs, neural network IP cores, and software tools for development, making it easier for developers to create and deploy AI/ML applications at the edge.
This session provides an overview of the Lattice sensAI solution stack for deployment of AI models onto Lattice FPGAs, it gives the latest update to the solution including learned step quantization, mixed precision (4/8-bit) , use of system generator to build SoC on FPGA fabric and improvement to sensAI studio training framework and simulator.
Level: Intermediate
Design of an SPI CONTROLLER to Control External DACs | Tutorial
plc2 GmbH
Description:
Design:
- Design of Wave Form Generator
- Design of an SPI CONTROLLER to control external DACs Verification (Test Bench)
- Modeling the external DACs
Hardware testing
Level: Beginner
Duration: 90 mins
12:45 - 1:30 pm
Lunch Break and Visit of the Exhibition
1:30 - 2:00 pm
KEYNOTE SPEECH
Edge AI Everywhere: How Platforms Can Reap Efficiency Benefits
Senior Director Customer Experience Engineering, Software and Solutions | AMD
Description
The continued amount of news on AI, particularly as it relates to training and data centers, is astounding. However, the opportunity for AI inference being used at the edge has been estimated to be even greater! Considering the sheer volume of devices that could be AI-enabled at the edge, this is certainly a credible assertion. For this to come to fruition, a huge investment is required in both embedded hardware and AI software for Edge AI to truly be “everywhere.”
For semiconductor companies to address this need, a platform approach is necessary for both. On the hardware side, a modular and scalable hardware approach is required to provide a range of solutions from tiny and cost effective to very high-performance. From a software perspective, a solution stack that leverages open-source AI frameworks and models and can span the full range of scalable hardware is needed to maximize developer productivity—so inference solutions don’t need to be exhaustively ported from one edge device to another. This combined platform approach can reap significant efficiency benefits for embedded developers targeting Edge AI devices across the spectrum of possibilities.
2:00 - 2:15 pm
Short Break and Option to Change Rooms
2:15 - 2:55 pm
It's not too late! From Component Testing, Quality Analysis and Component Preparation to Long-Term Preservation | Application
HTV Halbleiter-Test & Vertriebs-GmbH
Description:
- Obsolescence
- Counterfeiting, manipulation
- Ageing processes, component testing
- Quality analyses
- Component processing
- Long-term conservation
Level: Beginner
Making Simple FPGA Testbenches – Utilising Important Quality Measures | Language / Debug / Verification
EmLogic AS
Description:
UVVM is the world’s fastest growing verification methodology and has been so since its introduction in 2015. The reason for this is the extremely simple testbench architecture you can achieve with UVVM, the very easy to understand – high-level commands – you can use, and the unique reuse friendliness. UVVM also comes with lots of free and open source interface models (BFMs and VVCs) for interfaces like UART, SPI, AXI, AXI-lite, AXI stream, Avalon MM, Avalon stream, I2c, GPIO, SBI, GMII, RGMII, Ethernet, and more. UVVM is developed in cooperation with ESA (the European Space Agency) and is increasingly used for both mission critical space projects and industrial safety applications – including various DO-254 certified projects.
This presentation will show the basics of UVVM, but will also explain how it significantly improves the FPGA quality through simple-to-use testbench mechanisms.
Level: Beginner/Intermediate
What’s in a Name: FPGA vs. Adaptive SoC | Architecture
AMD
Description:
Programmable logic based devices have evolved over the years from I/O expansion devices to high-performance digital signal processors—through to full fledged systems on chips, also known as adaptive SoCs. This evolution has led to the development of devices capable of single-chip intelligence, where all the major processing stages of an AI system—preprocessing, AI inference, and postprocessing—can be done in a single, highly secure adaptive SoC. The technology to enable this level of innovation and integration is enormous. It includes significant hard IP from multiple heterogeneous processor types in addition to the latest high-speed interfaces, the latest security measures, and tools to support heterogeneous processor software development, system-level software integration and debug, and application software including inference models and soft IP. This presentation will provide an overview of the technology challenges and implementation strategies to accomplish single-chip intelligence.
Level: Beginner
Next-Generation Cybersecurity Strategic Shielding for Fortifying EU Infrastructures | Safety & Security
ASMY Software Group
Description:
The European Union is confronted with an increasingly complex and persistent cyber threat landscape, where critical infrastructures across sectors such as energy, finance, healthcare, and transportation are prime targets for malicious actors. As these infrastructures become more interconnected and dependent on digital technologies, the potential impact of cyberattacks on the EU's economy, public safety, and national security grows significantly and Cybersecurity attacks have become more sophisticated by using advanced techniques to bypass traditional defenses. To address these challenges, a comprehensive and forwardlooking cybersecurity strategy is essential. The proposed project aims to develop and deploy Next- Generation Cybersecurity Strategic Shielding (NGCSS) solutions to fortify EU infrastructures against evolving cyber threats.
The Next-Generation Cybersecurity Strategic Shielding project represents a vital step toward enhancing the security, resilience, and reliability of digital services and critical systems across the EU. By utilizing advanced technologies, fostering collaboration, and adopting a proactive and holistic approach to cybersecurity, the project aims to safeguard the EU's strategic interests, promote innovation, and protect citizens' rights in the digital age.
This proposal seeks to pioneer the detection of a new generation of cybersecurity attacks and explore the implementation of innovative algorithms that will contribute to the development of an advanced cybersecurity management framework within the EU. These AI and machine learning-based algorithms will include software components specifically designed to detect and counteract attacks in infrastructure environments. The goal is to strengthen these infrastructures while incorporating advanced functionalities like data recovery, ensuring a comprehensive approach to cybersecurity across EU countries.
Level: Beginner
Mix and Match – FPGA-Based AI Inference and Acceleration Using Quad Core RISC-V | AI / ML
Efinix GmbH
Description:
The idea of RISC-V-based AI implementation in Efinix FPGAs has been introduced and continuously developed over the past three years. An ease-of-use ECO system for deployment and acceleration of neural networks on FPGAs with lowest power, smallest size and high performance has been made possible with Efinix TinyML. While the solution in the beginning was based on Sapphire – at that time Efinix’ single core RISC-V soft IP – the most recent updates and upgrades in hard- and software extended the range up to Topaz and Titanium FPGAs with hardened Quad Core RISC-V.
The Quad Core processor now enables other interesting approaches, not only “even faster”. This presentation will focus on how single or multiple AI tasks can share the quad core resources and accelerators with each other, but also how these tasks can be combined with other system tasks running in parallel. A final summary gives an insight what this means in terms of performance, power consumption and also the size of the solution.
Level: Intermediate
Design of an SPI CONTROLLER to Control an External ADC | Tutorial
plc2 GmbH
Description:
Design:
- Design of an SPI CONTROLLER to control an external ADC Verification (Test Bench)
- Modeling the external ADC
Hardware testing
Level: Beginner
Duration: 90 mins
2:55 - 3:05 pm
Short Break and Option to Change Rooms
3:05 - 3:45 pm
A Cuckoo Hash-Based CAM Architecture for FPGA and ASIC Implementations | Application
CAST Inc.
Description:
This presentation introduces a Content-Addressable Memory (CAM) architecture which is based on Cuckoo hash-based algorithm and is tailored for FPGA and ASIC implementations. The proposed architecture is a constituent part for many network applications, such as high-speed IP filtering and flow classification. The architecture of the proposed Cuckoo hash-based architecture is demonstrated, and FPGA implementation details are presented. Furthermore, the employment of the proposed CAM architectures in the context of TCPIP network stacks is also discussed.
Efficient CAM designs are of particular research and practical interest for several reasons. CAMs are a fundamental part of hardware network stacks, and they serve various objectives. Furthermore, they usually lie in the maximum-delay critical path of hardware implementations, reserve a considerable area budget, and contribute substantially to power dissipation.
CAM operations closely resemble those in hash tables. Hash tables are commonly employed for retrieving a value that is associated with a related key, forming a key-value pair. The key is used as an index to locate the relevant value. The challenge in this process lies to the fact that multiple keys may lead to the same memory position, leading to collisions during the saving process. If the first memory position is occupied by another pair, the subsequent position is examined until an empty position is found. The second position is determined by a hash that is generated by a different hash function. The alternative position may lie in the same or another memory block. In the general case, a memory position can include multiple slots.
In this context, there is a trade-off between the complexity of save operations vs. the complexity of the search/erase operations. Hash-based schemes reduce the latency of search and erase operations at a corresponding cost of save operations. Most of the proposed hash-based designs employ two or multiple hash functions that generate the memory addresses to be checked for potential empty slots. To reduce latency and area, hash values are produced by non-cryptographic hash functions. Typical implementations include the Murmur, Jenkin, or XOR-based hash functions.
Level: Beginner
FPGA Requirements Tracking and the Requirements Traceability Matrix | Language / Debug / Verification
EmLogic AS
Description:
Requirements Tracking (aka Specification Coverage) is mandatory for any safety (e.g. DO-254) and mission critical (e.g. space) products. This is in fact required for any high quality product. Requirements tracking normally also involves reporting a so-called Requirements Traceability Matrix (RTM).
The level of ambition for Requirements Tracking depends on the application, and thus so does the RTM. This presentation will explain the RTM and different levels of Requirements Tracking. We will also show how the results can be presented and discuss some general challenges. Tracking FPGA requirements and generating the RTM can be very time consuming and boring when done manually and should thus be automated. There are expensive tools available that can handle this perfectly well, but there are also free and open-source tools available. We will look at one quite common simple solution and then finally how the open source UVVM can handle this for VHDL testbenches.
Level: Beginner/Intermediate
From Versal Adaptive SoC to 2 Gen Versal Portfolio | Architecture
plc2 GmbH
Description:
With the Versal Adaptive SoC quite some new features and design approaches have been introduced into the PS / PL devices from Zynq legacy. We will revisit these concepts and extrapolate into the brand-new Versal subfamilies Gen 2 variants and highlight the new additions. From the up-scaled compute power in the new Processing System to expanded safety features to the new IPs for multimedia processing or high speed interfaces, the application for Versal devices just expand even more. As available we share Versal tool flow insight.
Level: Beginner/Intermediate
Building a Secure System Leveraging FPGA-Based Hardware Root-of-Trust and Secure Boot | Safety & Security
Xiphera Ltd.
Description:
Establishing digital trust on a computing platform benefits from hardware root-of-trust (HW-RoT) and secure boot components situated on the computing platform itself. Examples of HW-RoT solutions include TPM, DICE, OpenTitan and Caliptra. Root-of-trust and secure boot can also be implemented in software. These example solutions and software implementations offer a wide range of security and cryptography services for a host system. However, the verification and validation of these solutions may prove challenging, especially when applied in high security assurance solutions. In addition, especially software implementations have multiple disadvantages compared to hardware based systems, for example longer boot-up times, deep SW stacks, key protection and other vulnerabilities.
In this presentation we establish a base for a secure system with essential hardware root-of-trust functions and how hardware based cryptographic solutions can be utilized to mitigate and even prevent threats of software vulnerabilities. We are going review the base requirements for a trustworthy boot sequence of a computing platform and introduce Post-Quantum Cryptography (PQC) schemes to provide future proof security. Finally, we suggest a foundation and architecture, which can be applied to FPGA based systems, to build hardware root-of-trust and secure boot for computing platforms.
Level: Beginner/Intermediate
Low-Power, High-Performance AI on Microchip FPGAs | AI / ML
Martin Kellermann & Brian Colgan
Microchip Technology GmbH
Description:
Microchip acquired Neuronix in 2024 to expand our capabilities for power-efficient, AI-enabled edge solutions deployed on FPGAs. The acquisition of this technology enables us to develop costeffective, large-scale edge deployments of components designed for use in computer-vision applications on systems that have cost, size and power constraints. Designers will be able to harness powerful parallel processing capabilities using industry-standard AI frameworks without in-depth knowledge of FPGAs.
Similar to a real brain, not every neuron has the same effect on the outcome of a recognition. “Classical” network-implementations not always take benefit of that, spending calculation time and energy on neurons with little contribution. With techniques as pruning and sparsity these networks can be improved on sizing, performance and power consumption.
In this session we will give an overview of how Neuronix’s AI technology is being incorporated into Microchip’s products and learn more about how Microchip enables the use of AI in designs.
Level: Intermediate
Design of an SPI CONTROLLER to Control an External ADC | Tutorial
plc2 GmbH
Description:
Design:
- Design of an SPI CONTROLLER to control an external ADC Verification (Test Bench)
- Modeling the external ADC
Hardware testing
Level: Beginner
Duration: 90 mins
3:45 - 4:30 pm
Coffee Break and Visit of the Exhibition
4:30 - 5:10 pm
The Right Engine for the Right Task: How to Achieve Real-Time, Determinism, and Mixed-Criticality in Robots | Application
AMD
Description:
This presentation will talk about how efficiently a roboticist can utilize the compute engines of adaptive SoCs and FPGAs. The idea is to use the right compute engine for the right task. The presentation will also describe how to achieve real-time, determinism, and mixed criticality in robotics using heterogeneous compute engines within the adaptive SoC. We will examine real challenges faced by robotists such as communication, separation/isolation, partitioning of the system, functional safety, cybersecurity, and industrial networking—and how to address them using the heterogeneous compute capabilities of an adaptive compute platform. We will also mention the open-source software framework on FPGA technology for roboticists known as the Kria robotics stack (KRS), which helps developers to work in a familiar Robotic Operating System 2 (ROS 2) environment but utilizing the advantages of FPGA technologies like high performance and low latency. We will discuss ROS 2 along with other important topics such as Micro-ROS, hypervisors, network offloading, functional safety, security, and industrial networking. Additionally, we will cover how simulation can enable hardware in the loop (HIL), digital twin, synthetic data creation, and large scale simulation environments to take advantage of FPGA technology.
Level: Beginner/Intermediate/Expert
Acceleration Techniques for FPGA Simulation and Debug | Language / Debug / Verification
Siemens EDA
Description:
FPGA simulation time increases and debugging becomes more complicated as designs get larger in size and functionality, accordingly time-to-market can be significantly delayed. When functional failures occur, speeding up design bring-up through effective and fast debugging techniques is essential. Performance improvement is necessary after having functionality intact. Accordingly, identification of bottlenecks using advanced profiling techniques will boost performance. Furthermore, designs can be qualified if they fit for multicore simulations, hence leverage speed ups.
This paper describes methods for efficient functional debugging to pinpoint actual root-cause in a speedy, yet accurate way. It also shows how to identify code hotspots and improve performance through time and memory profiling Finally, the paper explores techniques to determine how to benefit from multi-core simulation over conventional single-core simulation and applying it, is also covered in this paper.
Level: Expert
Elevate your Design: Security and Power Efficiency with AMD Spartan UltraScale+ FPGAs | Architecture
AMD
Description:
Hardware designers developing embedded applications have long faced challenges in optimizing cost, I/O density, and power efficiency. The AMD Spartan™ UltraScale+™ FPGA cost-optimized family addresses these challenges by offering innovative architectural solutions for a wide variety of applications, including edge sensing and control, machine vision systems, and board management control.
Key Highlights for This Session:
- Learn how to map application requirements to an ideal device, including trade-offs between I/O, power, and cost
- Utilize strategies to accelerate time to market with proven design tools, reducing development cycles
Join us to discover how the Spartan UltraScale+ FPGA can advance your next design, offering a powerful blend of I/O flexibility, low power, and state-of-the-art security features to meet evolving application demands.
Level: Beginner/Intermediate/Expert
From Bit Flips to Bulletproof: Radiation Hardening in FPGA Technology | Safety & Security
Arrow Central Europe GmbH
Description:
Radiation hardening is a critical consideration for electronic systems operating in high-radiation environments such as space, nuclear facilities, and defence applications. Field-Programmable Gate Arrays (FPGAs) are increasingly used in these domains due to their reconfigurability, high performance, and parallel processing capabilities. However, they are vulnerable to radiation-induced faults, such as Single Event Upsets (SEUs) and Total Ionizing Dose (TID) effects, which necessitate specialised mitigation techniques.In this session, we will explore the challenges of radiation effects on FPGAs and various hardening strategies. We will also compare the trade-offs between COTS (Commercial off-the-shelf) FPGAs and rad-hard variants, examining their suitability for critical applications.
Level: Beginner
ML Inference Compiler for FPGAs | AI / ML
SiWave Semiconductor Corporation
Description:
Introduction of a high level app to automate the implementation of ML inferences on FPGA. The tool doesn't require any prior knowledge or experience in FPGA design and can generate a final FPGA image by defining a couple of system parameters.
Level: Beginner
Band Pass Design | Tutorial
plc2 GmbH
Description:
Design:
- Band pass design Verification (Test Bench)
- Overall simulation
Hardware testing
Level: Beginner
Duration: 90 mins
5:10 - 5:20 pm
Short Break and Option to Change Rooms
5:20 - 6:00 pm
The Robot Revolution | Application
Martin Kellermann & Brian Colgan
Microchip Technology GmbH
Description:
The world of robotics is constantly chasing after the ideal machine, one that’s powerful yet nimble. Imagine a robot that can handle heavy lifting on a construction site while still being lightweight and energy efficient enough to operate for long hours without recharging. Striking this balance between brawn, brains and power efficiency remains a major hurdle in robotics development.
In this session we will go into detail on robotics and motor control solutions using Microchip FPGAs, including our multi-axis motion control solutions and how to improve productivity in motor control applications using C++ with HLS.
Level: Intermediate
Let's Use VHDL-2019 | Language / Debug / Verification
plc2 Design GmbH
Description:
Some VHDL-2019 features have finally arrived at first synthesis tools like AMD Vivado. This presentation will investigate how VHDL records can be upgraded to so called “mode views”. In short, a mode view is a “record with directions”. Thus, users will be very fast in wiring components by hand in an editor. Moreover, mode views can be applied to arrays too allowing users to apply for-generate loops on complex data buses.
Level: Intermediate/Expert
Faster Change of Probe Signals using the Vivado Logic Analyzer | Architecture
plc2 GmbH
Description:
By using the Vivado ECO flow, it is possible to modify existing ILA debug probes in the design, in a fast way.
After taking a general look at the Vivado ECO flow, we will concenctrate on how to use it regarding existing ILA debug probes.
In this session you will learn how to implement an ILA core into the design from scratch and how to modify the implemented debug probes using the Vivado ECO flow. The complete flow will also be shown in a live demo.
Level: Beginner/Intermediate
Mitigating Fault Injection Attacks in Multi-Tenant FPGAs: Detection and Response Mechanisms | Safety & Security
Karlsruhe Institute of Technology (KIT)
Description:
The increasing adoption of multi-tenant FPGAs in cloud computing environments introduces significant security risks, particularly fault injection attacks that compromise system reliability and data integrity. In this talk, we analyze the threat of power-hammering attacks, where malicious tenants induce voltage fluctuations within the FPGA's power distribution network (PDN) to disrupt neighboring workloads, cause computational errors, or even trigger denial-of-service (DoS) conditions.
To counteract these threats, we present two security mechanisms:
- LoopBreaker, a real-time mitigation technique that dynamically deactivates malicious FPGA partitions using partial reconfiguration. By continuously monitoring power consumption and detecting anomalies indicative of power-hammering, LoopBreaker ensures rapid response with minimal impact on benign workloads.
- Meta-Scanner, an offline security framework that leverages machine learning to analyze FPGA bitstreams before deployment. By classifying designs based on extracted metadata, Meta-Scanner proactively identifies potentially harmful configurations, preventing attacks before they occur.
Our evaluation on a Xilinx ZCU102 FPGA demonstrates that LoopBreaker reduces attack success rates by over 98.2%, while Meta-Scanner achieves a detection accuracy of 99.3% with minimal computational overhead. These results highlight the effectiveness of combining real-time countermeasures with proactive security analysis to safeguard multi-tenant FPGA cloud infrastructures.
This talk is intended for researchers, cloud security engineers, and FPGA developers seeking to understand emerging security risks in FPGA-as-a-Service (FaaS) platforms and explore robust countermeasures against fault injection threats.
Level: Intermediate/Expert
Intelligent Cameras: AI-Infused Image Signal Processing | AI / ML
Altera
Description:
Most modern cameras are underpinned by some form of intelligence, from a rudimentary tuning of image signal processor (ISP) parameters for constrained setup to automatic control of exposure, color balance, and focus (3A) for changing environments. Traditionally, such mechanisms are based on computer vision-based algorithms that analyze the scene based on abstracted numerical indicators (histograms, statistics, etc.). Recent advances in ML accelerators enabled on-the-fly content analysis. Such processing has conventionally been performed on fully processed RGB images and used to perform various object detection and recognition functions for security, video conferencing, automotive, and other end-user applications. However, enabled by FPGAs close NPU+ISP integration, flexibility in “tapping” points, and network-optimized architectures unlocked natural synergy between image processing and AI. This presentation will discuss a smart camera solution with a native AI inference engine and flexible imaging pipeline integration to use in-depth content analysis and salient feature extraction to fine-tune existing ISP parameters for target human or machine vision applications. Specifically, we describe how to utilize state-of-the-art object detection and segmentation to control such parameters as tone mapping, spatial and temporal noise reduction, 3A, image stabilization, and more. We also explore options to use AI to perform imaging functions, such as upscaling, debayering and depth estimation.
Level: Intermediate
Band Pass Design | Tutorial
plc2 GmbH
Description:
Design
- Band pass design Verification (Test Bench)
- Overall simulation
Hardware testing
Level: Beginner
Duration: 90 mins
from 7:00 pm
THE FPGA Conference 2025 - Evening Event
Celebrate with us in a relaxed atmosphere, with chilled drinks, delicious food and musical ambience. Use our evening event for extensive networking with the participants, speakers and partners. Looking forward to seeing you there!
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