Program 2025 - DAY TWO *
3 Days – 9 Thematic Focus Tracks – 100 Percent Knowhow
9:00 - 9:40 am
101 – Timing Closure | Application
plc2 GmbH
Description:
This session is about how to define proper timing constraints for a FPGA design from scretch.
During the session we will talk about where to start and how to proceeed throughout the complete process of defining timing constraints for the complete FPGA design. It will be presented which useful reports and timing analyzing features Vivado is offering to the FPGA designer.
At the end of the session, a live demo summarizes the complete procedure.
Level: Beginner/Intermediate
Mixed Verification: Regression Simulation Testbench with UVM for RTL Modules in VHDL | Language / Debug / Verification
INDRA SISTEMAS SA
Description:
In Europe, VHDL is widely used for designing RTL (Register Transfer Level) modules and has been predominant in the hardware design industry for many years. Many engineers are highly proficient in VHDL, as it has long been one of the most commonly used hardware description languages in digital circuit design projects. As a result, many projects, especially in sectors like automotive, aerospace, and defense are written in VHDL. However, when it comes to verifying these RTL modules, working exclusively in VHDL may not fully leverage the advanced features offered by modern verification languages and technologies like SystemVerilog and UVM (Universal Verification Methodology). Additionally, using UVM with Object-Oriented Programming (OOP) helps shift the mindset from RTL design to verification. By adopting a mixed verification approach, combining VHDL for RTL design with SystemVerilog and UVM for verification, engineers can take advantage of these advanced features without abandoning their expertise in VHDL. This approach leads to improved testbench efficiency, better validation of designs, and faster debugging times. Our presentation shows the design of a regression testbench with a self-checking methodology. A regression testbench automatically runs multiple test scenarios to verify the design. This ensures that recent changes, such as code updates or new features, do not negatively impact the existing functionality of the DUT, and allows for identifying potential issues early on. A self-checking testbench ensures the correctness of the RTL without manual intervention. Using SystemVerilog and UVM, this process becomes more streamlined. UVM components like uvm_monitor, uvm_driver, and uvm_scoreboard help create a testbench to compare results against a reference model, all while automatically reporting discrepancies. This self-checking approach eliminates the need for detailed, manual checks in the testbench. In essence, adopting mixed verification with SystemVerilog and UVM not only allows engineers to continue working in VHDL but also introduces the power of modern verification techniques. This results in more efficient, scalable, and maintainable testbenches, improving the overall quality and speed of the verification process, and ultimately leading to better-validated RTL designs.
Level: Beginner
MicroBlaze V Now! - The Way to Run RISC-V on AMD Hardware | Embedded / Vision
Avnet Silica
plc2 GmbH
Description:
We see more and more features now that will support even more tools and runtime environments (OS). Moving to the open source world is a win win for vendors and developers as well.
Bringing the future proof concept of open source from software to hardware.
Reducing maintenance effort to lower total cost of ownership in your projects.
- Intro & update to MicroBlaze-V
- RISC-V core variants
- Customizing core & system
- Hardware aspects
- RTOS, OS & tool support
- Using Vitis for RISC-V development
- Questions & answers
Participation to this seminar will enable you to start your next softcore project on AMD hardware. We will show the latest IP and tool capabilities which are available now.
Level: Intermediate
Duration: 90 mins
Integrating Adaptive Computing in Robotics: A Deep Dive into the AMD Kria Robotics Stack | Tools & Methodologies
AMD
Description:
This presentation will provide insights into the AMD Kria™ robotics stack (KRS), which is an open-source framework built on top of Robot Operating System 2 (ROS 2). KRS is an integrated set of libraries and utilities designed to enhance the performance of a robotics application using adaptive compute and accelerate development time by leveraging ROS 2. As we know, robots need very high-performance computing and low-latency communication, and for such applications, FPGAs are well suited. Algorithms implemented on FPGAs can easily scale to meet performance requirements while also delivering predictable and consistent execution. On the other hand, ROS 2 provides robot developers with a standard software platform that facilitates development from research to production, offering tools, libraries, and capabilities to shorten time to market. The KRS brings the benefits of both: the development of high-performance deterministic algorithms using FPGAs, and ROS 2 for a quick time to market.
In this presentation, we will explain:
- How a developer can write a ROS 2 application and accelerate their custom logic on an FPGA using HLS programming.
- How to integrate a ROS 2 application with the AMD Vitis™ Library, which is a set of accelerated functions based on HLS and provided as open source by AMD.
KRS aims to support the growing demand in the robotics sector, which is projected to expand significantly in the coming years. In summary, it is a comprehensive platform that empowers developers to create advanced robotic applications efficiently, leveraging AMD adaptive computing technologies.
Level: Beginner/Intermediate/Expert
Warning! Your FPGAs & SoC FPGAs are Under Attack | Safety & Security
HandsOn Training
Description:
FPGAs are increasingly being used in sensitive applications. Examples include our national infrastructures (power grids, network routers, satellites), transportation (planes, trains, automobiles), military equipment (weapons, radar, software defined radio) and medical devices. Unfortunately, as FPGA hardware continues to become more powerful and cheaper, it also becomes more attractive to attackers to attempt and exploit any security weakness in them. Such attacks have serious consequences. They can steal confidential information, modify the system to perform devious, unintended activities, perform denial of service, or even destroy the system. Therefore, securing is of utmost importance! Unfortunately, the security of FPGA has largely been ignored (until recently). In this lecture we discuss the modern attack techniques against FPGAs & SoC FPGAs.
Level: Beginner
OSVVM’s Test Reports and Requirements Tracking | Tutorial
SynthWorks Design Inc
Description:
FPGA verification engineers spend 47% of their time debugging. As a result, we need test reports that simplify debug and help find problems quickly. In addition, these reports were designed to provide you with the information needed for safety critical markets, such as space and DO-254 in mind.
OSVVM's test reports provide another reason why you should be using OSVVM. The reports
include:
- Build Pass/Fail Summary (text)
- Detailed Build Summary Report with completion status of each test case (HTML)
- JUnit report for continuous integration tools (XML)
- Detailed test case report that summarizes Error, Functional Coverage, and Scoreboard activity
- Requirements Tracking Report
- Simulator log files (simulator output) (HTML and text)
- VHDL test case output (text)
- Links to tool generated code coverage reports
This "how-to" tutorial provides the details of the scripting and VHDL code required to generate the reports.
OSVVM's reports are essential to find and fix issues while developing OSVVM - our regressions have 852 test cases in 45 test suites that produce a 1.4M line text log file. A reduced set of regressions is run on GitHub using GHDL and NVC. See
https://github.com/OSVVM/OsvvmLibraries/actions.
Level: Beginner
Duration: 90 mins
9:40 - 9:50 am
Short Break and Option to Change Rooms
9:50 - 10:30 am
Circuit Design | Application
plc2 GmbH
Description:
At first, we will talk about combinatorial and clocked circuits. After that, asynchronous and synchronous circuits are compared and explained. When talking about synchronous circuits, the clock distribution inside the FPGAs is very important. Because of that, it is explained how the clocking structure inside the FPGA is implemented and how to use it. After talking about general design guidelines, there will also be a demo at the end of this session.
Level: Beginner/Intermediate
FPGA Design Debugging... How Hard Can It Be? | Language / Debug / Verification
Brightelligence sp. z o.o.
Description:
FPGA design debugging is often more complex than it first appears. There are numerous reasons why an FPGA design might fail, and pinpointing the exact cause can be a daunting task. Issues may arise from a variety of sources: hardware malfunctions, faulty software, broken or flawed logic, synchronization issues, incorrect clock frequencies, missing or incorrect timing constraints, or even race conditions in asynchronous signals. While some of these problems may be deterministic, making them somewhat easier to isolate, non-deterministic bugs—those that appear sporadically and unpredictably—are far more difficult to track down and fix.
Each type of design issue requires a unique approach to find and address the root cause of improper behavior. A deterministic bug might be caught with simulation and proper test coverage, but non-deterministic issues, like glitches or metastability in asynchronous signals, may require specialized tools and techniques, such as inserting logic analyzers or using formal verification. Timing violations or clock domain crossing (CDC) issues may need timing analysis tools and careful review of constraints.
On top of these debugging challenges, there are system limitations that can further complicate the process. Some common limitations include:
- lack of test I/Os
- no JTAG connectivity
- overuse of resources (e.g. LUT, registers, block memory, routing)
- multiple chip design
- real-time dependencies (e.g. PCIe bootup).
Such additional constraints only increase the difficulty of identifying and fixing bugs, as they limit your ability to observe and interact with the design in real time.
Given the complexity of FPGA design and the potential for system limitations, you may wonder: How can we prevent bugs from occurring in the first place? How can we debug designs efficiently? Which techniques are most practical, and what is the best overall debugging methodology? We will answer these questions and others that you may have at the presentation.
Level: Intermediate
MicroBlaze V Now! - The Way To Run RISC-V on AMD Hardware | Embedded / Vision
Avnet Silica
plc2 GmbH
Description:
We see more and more features now that will support even more tools and runtime environments (OS). Moving to the open source world is a win win for vendors and developers as well. Bringing the future proof concept of open source from software to hardware.
Reducing maintenance effort to lower total cost of ownership in your projects.
- Intro & update to MicroBlaze-V
- RISC-V core variants
- Customizing core & system
- Hardware aspects
- RTOS, OS & tool support
- Using Vitis for RISC-V development
- Questions & answers
Participation to this seminar will enable you to start your next softcore project on AMD hardware. We will show the latest IP and tool capabilities which are available now.
Level: Intermediate
Duration: 90 mins
Vitis Functional Simulation: A Unified Framework for AI Engine and HLS Design Validation | Tools & Methodologies
N.N.
AMD
Description:
The AMD Versal™ heterogeneous architecture combines traditional programmable logic with a new compute engine, AI Engine, available in several of its series. The AI Engine accelerates data processing and machine learning applications. Validating such systems requires efficient simulation frameworks that can model each engine and the interactions between them. AMD Vitis™ Functional Simulation provides a unified environment for functional validation, supporting both MathWorks MATLAB® and Python™ environments. Vitis Functional Simulation enables designers to verify algorithmic correctness before hardware deployment. This session presents the core architecture of Vitis Functional Simulation and its role in accelerating developing applications running on AI Engine and programmable logic for ML and DSP applications.
Level: Intermediate
Functional Safety for Hardware and Software | Safety & Security
Microchip Technology
Green Hills Software
Description:
Safety-critical systems often contain FPGAs to add hardware flexibility, e.g. to accommodate for specification changes, interface adaptations or other functions that can more easily be implemented in hardware. For this, FPGA vendors provide support-packages dedicated to functional safety. With their immunity to single-event upsets Microchip FPGAs are a natural fit for these applications. Typically, a functional safety solution combines hardware and software, with mutual dependencies to fulfil the system’s safety requirements. Dedicated processors explicitly designed for certain safety-levels exist in the market, however these lack the flexibility of an associated FPGA-fabric. FPGA-based SIPs or SoCs are typically built as “quality managed” (QM) devices, i.e. they are not meant or certified for a higher safety integrity level. The question remains, how to run safety-critical software on these devices in order to build a safe and certifiable system?
Microchip together with Green Hills Software will explain how to bring safety into the QM-part of a FPGA-SoC processing system, run safety-critical software on top of it, and eventually allow to build diverse and safe systems.
Level: Intermediate
OSVVM’s Test Reports and Requirements Tracking | Tutorial
SynthWorks Design Inc
Description:
FPGA verification engineers spend 47% of their time debugging. As a result, we need test reports that simplify debug and help find problems quickly. In addition, these reports were designed to provide you with the information needed for safety critical markets, such as space and DO-254 in mind.
OSVVM's test reports provide another reason why you should be using OSVVM. The reports
include:
- Build Pass/Fail Summary (text)
- Detailed Build Summary Report with completion status of each test case (HTML)
- JUnit report for continuous integration tools (XML)
- Detailed test case report that summarizes Error, Functional Coverage, and Scoreboard activity
- Requirements Tracking Report
- Simulator log files (simulator output) (HTML and text)
- VHDL test case output (text)
- Links to tool generated code coverage reports
This "how-to" tutorial provides the details of the scripting and VHDL code required to generate the reports.
OSVVM's reports are essential to find and fix issues while developing OSVVM - our regressions have 852 test cases in 45 test suites that produce a 1.4M line text log file. A reduced set of regressions is run on GitHub using GHDL and NVC. See
https://github.com/OSVVM/OsvvmLibraries/actions
Level: Beginner
Duration: 90 mins
10:30 - 11:15 am
Coffee Break and Visit of the Exhibition
11:15 - 11:55 am
Breaking the Electron-Photon Barrier Using FPGA technology | Application
Niek van Agt & Dirk van den Heuvel
TOPIC Embedded Systems
Description:
As the computational world is moving towards the tera-hertz clock boundary, the processing of data in the photonic domain becomes more and more feasible. TOPIC Embedded Systems collaborates with a specialist in Fully Homomorphic Encryption (FHE) using photonic processing technology to create an advanced, quantum-resilient cryptography application. The vast amounts of data that are processed by the FHE engine puts high demands on the applied AMD FPGA technology and especially the RFSOC infrastructure and the GTM transceivers. During this presentation, you will learn about the complexity of the physical domain crossing, why this technology is very relevant and how the FPGA interfaces and fabric are being pushed to their limits to make the data flow as required.
Level: Intermediate
CAVEAT – An Open-Source Framework for Context-Aware Verification, Emulation, and Training | Language / Debug / Verification
University of New Brunswick
Description:
The operational requirements of academic environments as well as development laboratories regularly change as a result of shifting scope of work and diversity of projects. Experiments and diagnostics typically rely on a combination of commercially available tools and custom-developed instrumentation.
They are unique in their purpose and configuration, and their operation requires technical expert knowledge. This creates a barrier for a wider science community that would benefit from their use. In addition, the deployment and location of an instrument increases the stakes, e.g. in case of operation in remote Arctic areas or space. Under such circumstances, physical access to hardware for maintenance, in-situ testing, and repair is costly at best. Furthermore, an operational error may result in long-term impact or fatal loss of a mission. For this reason, preventative and proactive testing prior to deployment is important for risk mitigation and cost control.
Level: Beginner
Introduction to the HPS Architecture and Tutorial on How to Build and Run Linux on an Agilex 5 | Embedded / Vision
Arrow Central Europe GmbH
Description:
Detailed explanation of the Quartus HPS system architecture (HPS, LPDDR4, etc.) and the Altera Agilex 5 boot process. Step-by-step instructions on how to build a custom Linux kernel for the Agilex 5, U-Boot and SDCard Image. Demonstration of the Linux boot sequence (subject to setup at the FPGA conference, or I will show a recording).
Instructions for setting up a secure SSH console to the Agilex5 Linux. We will provide a script for anyone to build the Linux at home later.
Level: Beginner
Empowering Designers: From MATLAB to Efinix FPGA | Tools & Methodologies
The MathWorks GmbH
Efinix GmbH
Description:
Join us for an insightful session at the FPGA Conference, where we delve into the synergy between Efinix's innovative low power and high-speed FPGA solutions and MathWorks' advanced Model-Based Design tools. This talk will be divided into two segments, offering a comprehensive overview of how these technologies can transform your design and deployment processes.
- Segment 1: Efinix FPGA Solutions Efinix will kick off the session by showcasing their cutting-edge FPGA technology, renowned for its flexibility, power efficiency, and performance. Discover how Efinix's unique Quantum™ architecture provides a scalable and adaptable platform for a wide range of applications, from edge computing to AI acceleration. Learn about their latest innovations that empower designers to overcome traditional FPGA limitations, enabling faster time-to-market and enhanced product capabilities.
- Segment 2: From Model to Code with Simulink and HDL Coder
In the second half of the talk, MathWorks will demonstrate how their Model-Based Design approach, coupled with HDL Coder, streamlines the path from algorithm development to FPGA implementation. Explore how MATLAB and Simulink models can be converted into efficient HDL code, ready for deployment on Efinix FPGAs. We will cover key applications such as Digital Signal Processing (DSP), Wireless Communications, Computer Vision, and Control Systems. Attendees will gain insights into the verification and validation processes that ensure robust and reliable FPGA designs, reducing development cycles and enhancing design accuracy.
This session will provide valuable knowledge for engineers and designers looking to leverage the combined strengths of Efinix FPGAs and MathWorks tools to optimize their development workflows and achieve superior design outcomes.
Level: Beginner
Security, Regulations and FPGA-Based Systems – How to Make Your System Secure | Safety & Security
Matthias Lai & Harald Friedrich
NewTec GmbH
Description:
Product requirements, connected devices and security requirements:
- How to develop secure systems for industrial, automotive or medical devices over the complete product life cycle from idea to decommissioning.
- Requirements, Security Risk Assessment, what assets to protect, Threat Analysis and Risk Assessment (TARA)
In this talk we’ll show practical tips how to cope with challenges and give guidelines to develop products, that comply with the different security standards and regulations
Level: Beginner/Intermediate/Expert
Development of a Wishbone Verification Component with OSVVM | Tutorial
SynthWorks Design Inc
Description:
Verification components are a fundamental part of an advanced testbench framework. This presentation provides a guided tour of the development of a transaction-based Wishbone Verification Component using OSVVM.
The presentation will work through the steps of building an OSVVM verification component:
- Identify Transactions the DUT interface supports
- Correlate the transactions with OSVVM’s Model Independent Transaction Library
- Create a basic blocking verification component to start functional testing
- Enhance the capabilities of the verification component as needed
- Developing verification components using OSVVM’s Model Independent Library
- Simplifies the development of the VC by using the transaction interface and API
- Simplifies writing test cases since many VC share the same transaction API
- Supports co-simulation
At the end of the day, OSVVM does not need a "Lite" version of our verification framework because we make writing verification components as simple as writing a procedure. Furthermore, any of OSVVM's growing library of verification components can be used as a template for getting started.
Level: Beginner
Duration: 90 mins
11:55 am - 12:05 pm
Short Break and Option to Change Rooms
12:05 - 12:45 pm
Enabling Space Missions | Application
Sundance DSP
Description:
This is a presentation about our experience of building an FPGA-based embedded system for sending to space. The main reason for using Polarfire FPGA is explained and also the change in manufacturing that is required to build such a system for sending to space is discussed.
Level: Expert
Maximizing Early Bug Detection with a Static and Advanced Linting Solution in a CI Flow | Language / Debug / Verification
Cadlog GmbH
Description:
The key to a successful FPGA Design, finished on time, is a well-planned design, verification and CI flow. It should be based on frequent design analyses, so bugs can be detected and corrected early in the design flow. Because one of the worst things that can happen is to find a bug in a design, that has already progressed far towards sign-off and design release. If that happens, the whole design and verification team will suffer long nights and weekends to find the bug with the risk of not meeting the schedule. Not to mention all the problems that all the teams experience who depend on the design code. So, maintaining a high level of code quality cannot be underestimated.
This presentation will show how a formal based static and advanced linting solution can help find potential problems early in the design cycle, even before the first testbench code has been written. Design reviews, which bind many people for a long time, can be done much more efficiently, with reproducible results, documented as reports. This approach can be extended into the CI flow to make sure nothing escapes into production, because it needs to go through the checks and if they fail, the built process will stop.
Level: Intermediate
DSP Block Based Soft-Processor FPU Design | Embedded / Vision
Altera, an Intel Company
Description:
The Altera Nios-V soft processor is Altera’s implementation of the RISC-V architecture, and successor to the proprietary NiosII processor. The change from a proprietary ISA that is designed for FPGA implementation, to a standardized ISA presents interesting design tradeoffs when targeting an FPGA. Full compliance with the standard limits opportunities for using hardened multipliers or DSP blocks in the FPGA fabric, but LE-based implementations have very high latency and therefore reduced performance in a pipelined RISC processor.
There is also the question of the extent to which tools such as Altera’s DSP Builder can be used for FPU implementation. Intended for implementing high-speed feed-forward signal processing logic in FPGAs, such tools have the advantage of thorough validation but the high latencies of the generated circuits limit pipeline occupancy when used in a typical pipelined RISC processor which gets its performance from short feedback paths.
All of these factors had to be balanced in designing a RISC floating point unit for an FPGA soft processor; this paper uses Nios V as a test case to examine the most important tradeoffs that designers must make when using FPGA DSP blocks within functional units of a RISC processor.
Level: Intermediate
Model-Based Design (MBD) for Intelligent Field Devices in Industrial Automation | Tools & Methodologies
Sokratel GmbH
The MathWorks
Description:
In the current landscape of MATLAB® Simulink®, no functionalities exist to exploit the full capabilities of Multi-Processor System on Chip (MPSoC) Hardware in one tool like for the AMD Ultrascale+ MPSoCs. This hardware can currently be controlled with generated code by MATLAB® Simulink® for ARM processors (Cortex-A53) and the FPGA. However, the user is limited to using Linux as the operating system on the Cortex-A53 processors and the use of Cortex-R5 processors is not supported. With precise consideration of customer requirements, Sokratel GmbH developed a commercial MATLAB® Simulink® Target (SIRIUS OS Target) as an all-in-one solution, allowing simultaneous usage of all processors and the FPGA. Furthermore, real-time capability is made possible by using FreeRTOS as operating system on the processors. Only one Cortex-A53 core uses Linux for management tasks. The SIRIUS OS Target allows users to further develop in their known MATLAB® Simulink® environment and to pursue the model-based design approach, now utilising the full potential of their hardware with one click.
In this demonstration, we would like to present the application-oriented example of a motor controller using the Kria™ KD240 Drives Starter Kit. The motor is controlled via a customized IP running on the FPGA that is generated with Mathworks software. In addition, our SIRIUS OS Target is integrated in the model and provides further features like data exchange with applications for monitoring and controlling on different cores. A Data Logger for external data analysis, industrial communication to external components, a Web HMI to monitor and change parameters during runtime are easy to integrate, as they are already included in the SIRIUS OS platform.
In this demonstration, we display the functionality of our software, illustrate its modularity and underline ease of use. The SIRIUS OS Target is currently already being used in high power converter control in the wind industry, but many other fields of application are conceivable as presented with this motor control. A wide variety of intelligent field devices could be used in the future.
Level: Beginner
Verify the Bits that Fly : A Demonstration of Bitstream to HDL Equivalence Checking | Safety & Security
Graf Research Corporation
Description:
We propose a verification tool chain designed to meet emerging safety and security requirements for FPGAs used in high-assurance critical systems by enabling equivalence checking that directly evaluates the design in the bitstream. The combination of Siemens Questa Equivalent FPGA (QEF) and Enverite PV-Bit establishes a rigorous method for verifying equivalence between hardware description language (HDL) source code and the final programming bitstream deployed on the FPGA. These tools address critical challenges in ensuring that the bitstream implements the designer's intent accurately and without errors, as required by ISO 26262, FPGA Level of Assurance (LoA) Best Practices, and other high assurance security and safety standards. In addition to standard verification use cases, we emphasize the novel application of "delta verification," enabling efficient re-certification of FPGA bitstreams after minor updates. By proving that changes are isolated to specific design aspects, delta verification accelerates the assurance process in highly regulated industries, such as automotive and aerospace.
The presentation explores how QEF and PV-Bit can be integrated into a sequential verification chain. QEF first establishes logical equivalence between the HDL and the gate-level netlist (GLN) produced by the synthesis process. PV-Bit then verifies both logical and physical equivalence between the GLN and the bitstream. Together, this tool chain provides robust evidence that the final FPGA configuration faithfully implements the original design, addressing risks of both accidental errors and malicious modifications. We illustrate this verification process using an example design: a dual-issue RISC-V CPU implemented on an AMD Xilinx Kintex UltraScale FPGA.
Level: Intermediate
Development of a Wishbone Verification Component with OSVVM | Tutorial
SynthWorks Design Inc
Description:
Verification components are a fundamental part of an advanced testbench framework. This presentation provides a guided tour of the development of a transaction-based Wishbone Verification Component using OSVVM.
The presentation will work through the steps of building an OSVVM verification component:
- Identify Transactions the DUT interface supports
- Correlate the transactions with OSVVM’s Model Independent Transaction Library
- Create a basic blocking verification component to start functional testing
- Enhance the capabilities of the verification component as needed
- Developing verification components using OSVVM’s Model Independent Library
- Simplifies the development of the VC by using the transaction interface and API
- Simplifies writing test cases since many VC share the same transaction API
- Supports co-simulation
At the end of the day, OSVVM does not need a "Lite" version of our verification framework because we make writing verification components as simple as writing a procedure. Furthermore, any of OSVVM's growing library of verification components can be used as a template for getting started.
Level: Beginner
Duration: 90 mins
12:45 - 1:30 pm
Lunch Break and Visit of the Exhibition
1:30 - 2:00 pm
KEYNOTE SPEECH
Learn About Altera's Strategy and Commitment in the FPGA Market
Fellow, Director of Programmable Architecture | Altera, an Intel Company
Description
A Leading FPGA Solution Provider with 40+ years of Innovation. Altera, an Intel Company, provides leadership programmable solution that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGA´s, CPLD´s, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provideteh flexibility to accelerate innovation. We will talk about Altera as the only scaled operationally independent company. The applications where FPGA have a fit for the European market and the future of Altera. As artificial intelligence (AI) applications continue to scale in complexity, we will show practical examples, including implementations in robotics and real-time edge AI systems, will illustrate FPGA-based solutions' low-latency processing benefits. The session will also highlight advancements in FPGA design methodologies that streamline development and deployment in AI workflows.
2:00 - 2:15 pm
Short Break and Option to Change Rooms
2:15 - 2:55 pm
Bugs, Bugs, Bugs, Everywhere Bugs - What We Have Seen in Real World Projects | Application
Patrick Lehmann & Navid Jalali
plc2 Design GmbH
Description:
This humorous talk will present bugs from various fields of applications. Even the simplest functions or features might be broken. We do not want to disclose them right now. So please stay tuned for our presentation and check if your beloved software, IP-core, IC is on our list.
Level: Beginner
Introduction to the VUnit Verification Framework | Language / Debug / Verification
Enclustra GmbH
Description:
This presentation introduces VUnit, a powerful open-source VHDL verification framework designed to streamline the FPGA development process. Targeted at beginners, it will explain what VUnit is, how it integrates with your workflow, and how it enhances verification efficiency. Attendees will learn how VUnit's automation capabilities, test structure, and built-in libraries help catch bugs early, improve test coverage, and reduce development time. By the end of the session, participants will have a clear understanding of how VUnit works and how it can be applied to their own FPGA projects for faster, more reliable results.
Level: Expert
A Fine-Grained Multi-Threading RISC-V for FPGA Systems | Embedded / Vision
Hochschule Osnabrück
Description:
In FPFA designs, it is often helpful to embed a processor for control tasks. For many years now, the RISC-V architecture has been widely used for this purpose, as it can be freely used as an open architecture and a wide range of implementations are also available. This talk presents a special RISC-V variant, a fine-grained multi-threaded processor. It is referred to as FGMT Risc-V in the sequel. The heart of this processor is a ramified processing pipeline with the usual stages: Fetch instruction, fetch operands, execute instructions and store results. It is realized as an AXI streaming pipeline, which inherently controls the flow of data through the individual stages. The program counter is fed in at the input of the pipeline and the modified program counter is emitted at the output. Internally, the individual stages ramify depending on the functionality of the respective instruction and are merged again at the output. The instruction and data memories are accessed via streaming interfaces on the side of the pipeline, which provide read and write access to the address space using request and response channels. The number of pipeline stages is not fixed; it can be adapted to timing specifications by inserting AXI-Streaming synchronization components. Such a pipeline is far from being fully utilized with a single program stream, therefore several program streams, each with its own program counter, are fed through the pipeline in the FGMT RISC-V. Each of these program streams therefore represents a separate thread and requires its own register set. The program counter is therefore extended by a thread identifier; these two values form a thread token. The thread identifier is used to assign each thread its own register bank in the processing pipeline. Single FPGA blockrams (4-32 kBit) can accommodate 4 to 32 register banks, in which case the same number of threads are permitted in the pipeline. In the FGMT processor, the processing pipeline is combined with infrastructure (thread launching, monitoring, interrupt and error handling, etc.) and a token FIFO to form a closed ring in which the thread tokens circulate. The ring incorporates components for manipulating the token stream, which also offer an interface for a debugger to enable source-level debugging in the system. As an example, a small system consisting of FGMT-RiscV with Wishbone bus, GPIO, Timer and UART running on an Evaluation board will be presented in the talk. Depending on the FPGA used, it occupies around 2000-4000 LEs. As an extra goodie, a GDBServer software is installed on the system as thread 0, which is directly connected to the GNU Debugger via serial interface and enables debugging of the processor's other threads.
Level: Intermediate
Tools and Techniques for Higher Design Efficiency | Tools & Methodologies
Lattice Semiconductor
Description:
Using Lattice Radiant software’s block-based design flow, virtual-I/O flow, and incremental design offers significant benefits for FPGA development. The block-based design flow enables modular design, facilitating reuse and faster timing closure. Using it as isolation design flow, It gives you as well benefits for end application having a safety requirement.
Virtual-I/O flow allows early software development and testing without complete hardware, accelerating the design cycle.
Incremental design supports partial reconfiguration, reducing compilation times and enabling efficient design updates.
You will learn on how to use this flows and how they benefit your design flow.
Level: Intermediate
When FPGAs Meet System Engineering | Board Design & Connectivity
The MathWorks GmbH
Description:
In today's fast-evolving technological landscape, FPGAs have become integral to complex systems, demanding a sophisticated blend of diverse domains and multiple levels of abstraction. The elaborate nature of FPGA development calls for structured engineering methodologies to ensure reliability and peak performance in their applications. Systems engineering principles are crucial for:
- Managing complex FPGA designs and requirements through comprehensive modeling
- Optimizing functionality allocation on FPGAs with effective techniques
- Ensuring functional correctness via robust validation and verification processes
- Accelerating deployment and reducing development time through efficient RTL code generation.
As FPGAs become essential in many heterogeneous designs, the role of systems engineering is increasingly critical to the success of development projects. This presentation will delve into the key systems engineering principles necessary for designing and implementing complex FPGA solutions, promoting a synergetic approach to integrating FPGA technology and systems engineering to create successful products.
Level: Beginner
FPGA Verification Architecture – The Key to Checking the Design Quality in an Efficient and Reusable Manner | Tutorial
EmLogic AS
Description:
For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification architecture is well-structured and developed with a focus on reuse. In this webinar, we will show you how to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture. We will also discuss the importance of testbench sequencer simplicity and how it can be used to control multiple VHDL Verification Components simultaneously.
Agenda:
- Testbenches with basic architecture and their limitations
- Components of an efficient and advanced testbench architecture
- VHDL Verification Components (VVC)
- Controlling and checking many interfaces simultaneously
- UVVM, VVC Framework Testbench Sequencer
- Conclusion
- Q&A
Level: Beginner/Intermediate
Duration: 90 mins
2:55 - 3:05 pm
Short Break and Option to Change Rooms
3:05 - 3:45 pm
Area & Power Reduction: Can You Beat The Synthesizer? | Application
HandsOn Training
Description:
FPGA designers encounter challenges which require deeper understanding of the design in order to optimize speed, area or power consumption. Natively, FPGA designers rely on writing high-level descriptions in HDL and let the synthesizer find the best solution based on the required optimization technique. However, the tools have many limitations, and the designer can get better results in case he is aware of various techniques and analysis methodologies. In this lecture we will explore different techniques such as resource and functionality sharing as well as alternative algorithms to reduce area and dynamic power consumption or increase speed without pipelining technique. The session will demonstrate various use cases and how to write HDL code that beat the synthesizer.
Level: Expert
Why VUnit? | Language / Debug / Verification
Aldec
Description:
In the realms of HDL code verification, where precision and efficiency are crucial, a great hero has emerged; VUnit. This open-source framework for VHDL/SystemVerilog has been making waves in the industry, offering a unique approach to verification that promises to revolutionize the way we test and validate HDL code.
In this seminar, we will explore how VUnit integrates seamlessly with comercial simulator, we guide you through creating a project from scratch, and demonstrate how to run multi-threaded unit testing, how to modify each testing approach to enhance your unit testing with VUnit even further, making it more intuitive to use. We propose solutions of integrate VUnit with other flows.
Level: Beginner
Efinix RISC-V Solutions from Soft to Hard | Embedded / Vision
Efinix GmbH
Description:
The RISC-V instruction set architecture (ISA) has rapidly gained recognition as a versatile and open standard, enabling FPGA & ASIC solutions that range from soft-core to hard-core implementations. In this session, we will explore the unique features and advantages of Efinix’s RISC-V architecture, with a focus on scalability and achieving the best computational power per milliwatt.
Efinix’s RISC-V solutions are well-suited for the entire product portfolio—Trion, Topaz, and Titanium—and are highly customizable and scalable. These solutions empower developers to optimize their designs for specific applications, with an emphasis on maximum performance and efficiency.
Join us in this presentation for a detailed guide and comparison of the different Efinix RISC-V customizations, ranging from the smallest footprint soft-core solutions to the highest-performance hardened RISC-V implementations.
Level: Intermediate
Open Standard Based High-Level Design Methodology for Near-Sensor Low-Latency Computing | Tools & Methodologies
Lattice Semiconductor
Description:
In this paper, we present how we implemented such a flow for low-power FPGAs using open standards for less cost. This is possible since we are focusing on the near-sensor low-latency edge systems for smart robots and factory automation instead of targeting general markets. This makes the proposed method optimized for applications for cost and power.
Level: Intermediate
Driving Next-Gen FPGA Performance: How MEMS Timing Powers Data Center, AI, and Industrial Innovation | Board Design & Connectivity
SiTime
Description:
Data center/AI, communication and industrial applications evolve to higher data rates, more deterministic and reliable data delivery.
A key to achieving these goals is more precise, lower latency synchronization and timing.
Achieving these goals relies on dedicated semiconductor timing devices combined with Precision Time Protocol (PTP) software stacks for accurate time distribution.
This technical session will showcase comprehensive timing solutions for FPGA-based applications, emphasizing how the latest MEMS technology enhances system performance by improving bit error rates (BER), achieving sub-nanosecond time alignment, reducing power consumption, lowering component count, and increasing overall system reliability and robustness.
Level: Intermediate
FPGA Verification Architecture – The Key to Checking the Design Quality in an Efficient and Reusable Manner | Tutorial
EmLogic AS
Description:
For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification architecture is well-structured and developed with a focus on reuse. In this webinar, we will show you how to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture. We will also discuss the importance of testbench sequencer simplicity and how it can be used to control multiple VHDL Verification Components simultaneously.
Agenda:
- Testbenches with basic architecture and their limitations
- Components of an efficient and advanced testbench architecture
- VHDL Verification Components (VVC)
- Controlling and checking many interfaces simultaneously
- UVVM, VVC Framework Testbench Sequencer
- Conclusion
- Q&A
Level: Beginner/Intermediate
Duration: 90 mins
3:45 - 4:30 pm
Coffee Break and Visit of the Exhibition
4:30 - 5:10 pm
Managing and Versioning Gateware Source Code on Git with Hog | Application
Max Planck Institute for Physics
Description:
Coordinating firmware development among many international collaborators is becomi
ng a widespread challenge. Hog (HDL-ongit) is a powerful set of Tcl/Shell scripts designed to facilitate the management of HDL c
ode for FPGAs with Git. It guarantees synthesis and Place and Route (P&R) reproducibilit
y and assures the traceability of output binary files. Key Features:
- Reproducibility: Full control over source and configuration files, ensuring consistent synthesis and P&R results.
- Traceability: Each binary firmware file embeds the git tag and commit SHA, allowing retrieval of the corresponding source code from the repository at any time.
- Continuous Integration (CI): Templates for setting up a CI workflow to build and simulate HDL projects using GitLab CI/CD or GitHub Actions.
- Compatibility: Works seamlessly with major HDL IDEs like AMD Vivado, ISE, Inte
l Quartus, and MicroSemi Libero.
This tutorial will demonstrate how to use Hog to manage a Vivado project on Git, showc
asing the following features:
- Convert an Existing Vivado Project to Hog: Step-bystep guidance on migrating a current project to Hog.
- Create and Build a Vivado Project with Hog: Detailed instructions on setting up and managing new projects using Hog.
- Setup a Hog CI with GitLab CI/CD and GitHub Actions: Implementation of continuous integration for automated builds and simulations.
Level: Intermediate
Enhancing FPGA Verification by Combining VUnit and UVVM | Language / Debug / Verification
P2L2 GmbH
Description:
This talk explores the synergy between VUnit and UVVM, two leading open-source verification frameworks for VHDL. UVVM provides a structured approach with powerful testbench utilities and verification components, while VUnit enhances automation, advanced test management, and continuous integration support. Additionally, VUnit enables seamless use of multiple simulators within a single project setup.
The session includes practical examples and best practices to demonstrate how combining these tools streamlines FPGA verification, improves productivity, and ensures maintainable and expandable testbenches.
Level: Beginner
RISC-V FPGA Soft Processor Implementations | Embedded / Vision
Altera, an Intel Company
Description:
There is a broader industry movement towards adopting RISC-V architectures in FPGA designs, driven by the demand for flexibility, customization, and the benefits of open-source ecosystems. The latest development and innovations in the Altera Nios V RISC V based soft processor implementation will be discussed.
Level: Intermediate
Reimagining FPGA Design: The Impact of Higher-Level Languages and AI | Tools & Methodologies
Eccelerators GmbH
Description:
The development of Field-Programmable Gate Arrays (FPGAs) is a complex task that requires expertise in digital design, low-level programming, and hardware-software integration. While traditional hardware description languages (HDLs) such as VHDL and Verilog provide precise control over the underlying hardware, they require extensive low-level knowledge and often lead to subtle, hard-to-detect errors when generated by large language models (LLMs). These shortcomings can negate potential productivity gains promised by AI-driven code generation. Higher-level language concepts, on the other hand, offer improved semantics and abstraction, thus reducing complexity and error rates. Yet, common high-level languages (e.g., C, Java, Python) were originally designed for CPUcentric, stack-based execution models, making their direct mapping to FPGA architectures both limited and cumbersome.
We indicate that it is beneficial to overcome the challenges of mapping high-level languages to FPGA architectures. By training LLMs on a domain-specific corpus of higher-level FPGA concepts, we demonstrate a marked improvement in hardware code generation accuracy, underscoring the value of a dedicated DSL approach for effectively mapping designs to FPGA architectures. Our results indicate that training LLMs on this domain-specific corpus significantly improves the correctness of generated hardware code, mitigating the pitfalls common in lower-level HDLs. This approach simplifies design workflows, boosts productivity, and reduces the need for exhaustive manual reviews. By bridging AI techniques with hardware-aware DSLs, we illustrate a pathway to more reliable and efficient FPGA development, ultimately highlighting the transformative role of higherlevel language concepts in the future of FPGA design.
Level: Intermediate
Practical Power Designs for New FPGA/SoCs | Board Design & Connectivity
TDK
Description:
This presentation will show power management engineers practical power designs for new FPGA/SoCs such as Altera’s Agilex 5 and AMD’s Versal Edge. Proven reference designs will be discussed. This presentation will also look into optimizing output filter design to meet the stringent transient response requirements of FPGAs via QSPICE and SIMPLIS and discuss SmartVID for Agilex via Intel Quartus.
Level: Intermediate/Expert
The Important Mechanisms to Assure a Good FPGA Quality Through Efficient Simulation | Tutorial
EmLogic AS
Description:
In this presentation, we will look at the most important aspects of FPGA verification that allow us to get the best possible quality with the least effort. Thus, the best possible ROI (Return On Investment) for various verification approaches, aspects and architectures.
ROI does of course differ a lot between different applications and between simple and complex DUTs, and it is important to know the pros and cons of different testbench architectures and aspects. This presentation will explain some typical problem scenarios, and how they could be handled in a structured testbench. We will also describe how complex verification can be significantly simplified using a structured approach, and how we can significantly improve overview, readability, maintainability, extensibility, debuggability and reuse.
Level: Intermediate/Expert
Duration: 90 mins
5:10 - 5:20 pm
Short Break and Option to Change Rooms
5:20 - 6:00 pm
A Baseboard Management Controller for FPGA/SoC Board Supervision and Faster Bringup | Application
Patrick Lehmann & Navid Jalali
plc2 Design GmbH
Description:
Complex mainboards with more then 50 power rails are not easy to startup, shutdown, or debug. Moreover, power sequencing ICs do not offer so many control channels. Usually, a software programmable Baseboard Management Controller (BMC) is used to provide the necessary functionality. This talk will present ideas and challenges while designing a STM32-based BMC software and how it interacts with the mainboard’s peripheral ICs.
Level: Intermediate
Open Logic – Open-Source FPGA Standard Library | Language / Debug / Verification
Enclustra GmbH
Description:
Open Logic is the fastest-growing open-source HDL standard library on the market, as measured by GitHub stars. It simplifies FPGA development with reusable, modular, and vendor-independent components. Bridging the gap between hand-optimized code and high-level abstractions like HLS and IP integration, it offers a balanced approach to effort and resource optimization. With a strong focus on code quality, verification, documentation, and ease of use, Open Logic ensures both reliability and accessibility.
This presentation will highlight the library's philosophy, its place in the FPGA design landscape, and the advantages it offers, including device independence and reduced maintenance effort. Attendees will explore key features such as FIFOs, AXI utilities, and CAMs, and discover how to integrate Open Logic effectively into their projects.
Level: Beginner
Adaptive RISC-V SoC for Industrial Edge AI Using Low power FPGA | Embedded / Vision
Lattice Semiconductor
Description:
This paper introduces a highly configurable RISC-V based FPGA System on Chip (SoC) designed for low-power and industrial edge AI applications. Leveraging advanced FDSOI technology and LUT4 architecture, the SoC achieves exceptional power efficiency, operating under 0.6W. This versatile soft SoC offers extensive customization, including configurable GPIO, DMA, control interfaces (I2C, SPI, UART), and reliable host connectivity via traditional tri-speed Ethernet, which are crucial for industrial SoCs. From a firmware perspective, it offers multi-OS support, including FreeRTOS, Zephyr, and bare-metal, alongside comprehensive software device drivers, ensuring rapid system bring-up and flexibility. Moreover, this design seamlessly integrates various memory subsystems like LPDDR4, DDR3, Flash, and RPC DRAM, and offers robust multi-boot capabilities. The common use cases for this SoC include applications in motor control, sensor fusion, and predictive maintenance, highlighting its potential in robotics and industrial automation.
Level: Intermediate
The Power of High Level Co-Simulation for HDL Designs | Tools & Methodologies
Ing. Büro Harald Simmler
Description:
Traditional HDL verification approaches use HDL with various libraries to apply stimulus to and validate responses from HDL designs. Since HDLs are not well suited for this, writing testbenches takes a lot of time which is rather spend on the design process.
A more efficient approach is to utilize open source Co-Simulation environments like Cocotb, enabling the HDL designer to write testbenches that cover an extensive amount of test combinations without a lot of effort and coding. Cocotb comes with a large variety of open source interface models for AXI, AXI-Lite, AXI-Stream, I2C/SPI, UART, PCIe and others, support various simulators and uses Python to command those. This combination leverages the high level approach of Python with the powerful simulation tools everyone is already familiar with.
The real potential is shown, when used in combination with standard Python libraries to prepare and validate HDL functionality. Such a high level Co-Simulation approach allows the designer to write complex testbenches with only a few lines of code. When used with generator tools for registers and testbenches it can reduce the time to a fully functional HDL testbench to just minutes. This will be be shown in a live demo.
Level: Intermediate
RFSoC RoCE Offload - 100Gbit RDMA on FPGAs | Board Design & Connectivity
FH Oberösterreich Studienbetriebs GmbH
Description:
Modern high-performance FPGAs can record or create data at ever-increasing rates.To transfer this data, high speed Ethernet IPs are integrated into many FPGAs. Often data needs to be transferred from the FPGA to a Computer for further processing on a CPU or GPU, or for storage. However, even state-of-the-art CPUs can struggle to process a single high-bandwidth data stream over the network in real-time. By leveraging standard RDMA technologies, we can offload network processing from the CPU and improve data throughput - without requiring FPGA-powered network adapters.
In this talk, we will present "RFSoC RoCE Offload", which demonstrates the power of RDMA by transmitting high sample rate ADC data over RDMA. Our design utilizes the RoCE (RDMA over Converged Ethernet) protocol, which provides RDMA capabilities over a standard Ethernet connection.
We will start the presentation by discussing the challenges high-bandwidth networking presents for CPUs. Next, we introduce the RoCE RDMA protocol, explaining how it can address these challenges and how it can be implemented on an FPGA. We will then outline the requirements for receiving data on a computer using a RoCE capable 100Gbit Ethernet adapter. Additionally, we will demonstrate how software can be adapted to transfer data directly to GPU memory for efficient, high-performance computation.
Finally, we will compare the performance and computational overhead of our RDMA-based system against traditional, non-RDMA approaches.
Level: Intermediate
The Important Mechanisms to Assure a Good FPGA Quality Through Efficient Simulation | Tutorial
EmLogic AS
Description:
In this presentation, we will look at the most important aspects of FPGA verification that allow us to get the best possible quality with the least effort. Thus, the best possible ROI (Return On Investment) for various verification approaches, aspects and architectures.
ROI does of course differ a lot between different applications and between simple and complex DUTs, and it is important to know the pros and cons of different testbench architectures and aspects. This presentation will explain some typical problem scenarios, and how they could be handled in a structured testbench. We will also describe how complex verification can be significantly simplified using a structured approach, and how we can significantly improve overview, readability, maintainability, extensibility, debuggability and reuse.
Level: Intermediate/Expert
Duration: 90 mins
* subject to change
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